The invention relates generally to the field of power over local area networks, particularly Ethernet based networks, and more particularly to a method of detection and identification of the connection arrangement of a powered device receiving power over four twisted wire pairs.
Power over Ethernet (PoE), in accordance with both IEEE 802.3af-2003 and IEEE 802.3at-2009, each published by the Institute of Electrical and Electronics Engineers, Inc., New York, the entire contents of each of which is incorporated herein by reference, defines delivery of power over a set of 2 twisted wire pairs without disturbing data communication. The aforementioned standards particularly provide for a power sourcing equipment (PSE) and a powered device (PD). The power sourcing equipment is configured to detect the PD by ascertaining a valid signature resistance, and to supply power over the 2 twisted wire pairs only after a valid signature resistance is actually detected.
U.S. Pat. No. 7,492,059 issued Feb. 17, 2009 to Peker et al, the entire contents of which is incorporated herein by reference is addressed to powering a PD over 4 twisted wire pairs. Such a technique provides for increased power as compared to either of the above mentioned standards, and is commercially available from Microsemi Corporation of Alisa Viejo, Calif.
The HD BaseT Alliance of Beaverton Oreg. has published the HDBaseT Specification Version 1.1.0 which defines a high power standard utilizing twisted wire pair cabling, such as Category 5e (CAT 5e) or Category 6 (CAT 6) structured cabling as defined by ANSI/TIA/EIA-568-A. The specification provides for even higher power than the above mentioned IEEE 802.3at-2009 over each set of 2 pairs, with all 4 pairs utilized for powering, and allows for power over structured communication cabling from any of: a type 1 PSE, denoted hereinafter as a low power PSE, typically meeting the above mentioned IEEE 802.3af standard; a type 2 PSE denoted hereinafter as a medium power PSE, typically meeting the above mentioned IEEE 802.3at standard; a type 3 PSE, denoted hereinafter as a high power PSE, typically meeting the above specification; twin medium power PSEs; and twin high power PSEs.
Detection, in accordance with any of the above standards requires the supply of at least 2 voltage levels between the range of 2.8 volts and 10 volts, with a signature resistance of the PD determined based on a calculation of the actual voltage levels, or current, detected. The use of 2 voltage levels allows for determination of the signature resistance irrespective of the existence of a diode bridge, typically supplied at the input to the PD. The voltage levels may be impressed via either a current source, or a voltage source.
FIG. 1A illustrates a high level block diagram of a PoE powering arrangement 10, according to the prior art, comprising: a switch/hub 20; a plurality of twisted wire pairs 30 constituted within a structured cable 35; and a PD 40. Switch/hub 20 comprises a plurality of data transformers 50 and a first and a second PSE 60 and a master control 63. PD 40 comprises: a plurality of data transformers 50; a first and a second diode bridge 65; a PD interface 70; an electronically controlled switch 80; and a PD load circuitry 90. PD interface 70 comprises: an under-voltage lockout (UVLO) circuit 100; a signature impedance 110; and a class current source 120. Optionally, a class event counter is further supplied (not shown). As illustrated in FIG. 1B, PSE 60 comprises: a control circuitry 61; a sense resistive element, illustrated and described herein without limitation as a sense resistor RS; and a current limiter CL, illustrated and described herein without limitation as an n-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET). Control circuitry 61 comprises: a detection functionality 62; a classification functionality 64; a powering functionality 66; and a maintain power signature (MPS) detection functionality 68, each of which may be constituted in a dedicated circuitry, or as a programmed functionality for a computing element, without limitation. Each control circuitry 61 is responsive to master control 63 (connection not shown). In one embodiment, a selected control circuitry 61 further acts as master control 63 and communicates commands to other associated control circuitries 61.
A data pair is connected across the primary winding of each data transformer 50 in switch/hub 20 and a first end of each twisted wire pair 30 is connected across the secondary winding of each data transformer 50 in switch/hub 20 via respective connections, listed conventionally in two groups: connections 1, 2, 3, 6, denoted ALT-A, where power is thus delivered over a first set of wires; and connections 4, 5, 7 and 8, denoted ALT-B, where power is thus delivered over a second set of wires. A first output of first PSE 60, representing the positive polarity, is coupled to the center taps of the secondary windings of data transformers 50 of switch/hub 20 connected to twisted wire pairs 30 via connections 1 and 2; and a return of first PSE 60, which as shown in FIG. 1B is associated with the drain of NMOSFET CL, is coupled to the center taps of the secondary windings of data transformers 50 of switch/hub 20 connected to twisted wire pairs 30 via connections 3 and 6. A first output of second PSE 60, representing the positive polarity, is coupled to the center taps of the secondary windings of data transformers 50 of switch/hub 20 connected to twisted wire pairs 30 via connections 4 and 5; and a return of second PSE 60, which as shown in FIG. 1B is associated with the drain of NMOSFET CL, is coupled to the center taps of the secondary windings of data transformers 50 of switch/hub 20 connected to twisted wire pairs 30 via connections 7 and 8. The powering arrangement associated with first PSE 60 is conventionally known as ALT-A powering, i.e. wherein powering is provided over the set of wire pairs associated with connections 1, 2, 3 and 6; and powering from second PSE 60 is conventionally known as ALT-B powering, i.e. wherein powering is provided over the set of wire pairs associated with connections 4, 5, 7 and 8.
The gate of NMOSFET CL is coupled to an output of control circuitry 61. The source of NMOSFET CL is coupled to a first end of sense resistor RS and a respective input of control circuitry 61. A second end of sense resistor RS is coupled to a respective input of control circuitry 61 and to a return line 130 coupled to a return of a power source (not shown). A power line 140, coupled to the power output of the power source (not shown) represents the positive polarity output of PSE 60. Structured cable 35 typically comprises 4 twisted wire pairs 30.
A data pair is connected across the primary winding of each data transformer 50 in PD 40 and a second end of each twisted wire pair 30 is connected across the secondary winding of each data transformer 50 in PD 40 via respective connections, listed conventionally in two groups: connections 1, 2, 3, 6; and connections 4, 5, 7 and 8. The inputs of first diode bridge 65 are respectively connected to the center taps of the secondary windings of data transformers 50 of PD 40 connected to twisted wire pairs 30 via connections 1, 2, 3 and 6. The inputs of second diode bridge 65 are respectively connected to the center taps of the secondary windings of data transformers 50 of PD 40 connected to twisted wire pairs 30 via connections 4, 5, 7 and 8. The positive outputs of first and second diode bridges 65 are commonly connected to the positive input of PD interface 70, and the returns of first and second diode bridges 65 are commonly connected to the return of PD interface 70. PD interface 70 is illustrated as having a pass through connection from the positive input to the positive output thereof, and power for each of UVLO circuit 100, signature impedance 110 and class current source 120 are provided there from (not shown). PD interface 70 is illustrated as having a pass through connection from the return input to the return output thereof, and a return for each of UVLO circuit 100, signature impedance 110 and class current source 120 are provided there from (not shown). Electronically controlled switch 80 is arranged to provide a switchable connection between the return of PD load circuitry 90 and the return of PD interface 70, and electronically controlled switch 80 is responsive to an output of UVLO circuit 100, indicative that received power is reliable and is denoted PG. The positive input of PD load circuitry 90 is connected to the positive output of PD interface 70.
Powering arrangement 10 has been illustrated in an embodiment wherein electronically controlled switch 80 is connected in the return path, however this is not meant to be limiting in any way and in another embodiment electronically controlled switch 80 is connected in the power path. Similarly, PSE 60 is illustrated as being part of switch/hub 20 however this is not meant to be limiting in any way, and midspan equipment may be utilized to provide a connection for PSE 60 without exceeding the scope. PSE 60 may be any equipment arranged to provide power over communication cabling, including equipment meeting the definition of a PSE under any of IEEE 802.3af; IEEE 802.3at; and the above mentioned HDBaseT specification, without limitation.
In operation, electronically controlled switch 80 is initially set to isolate PD load circuitry 90 from PSE 60. Each of first PSE 60 and second PSE 60 acts to detect PD 40 utilizing detection functionality 62 in cooperation with signature impedance 110 presented by PD interface 70. After detection, PSE 60 optionally presents a classification voltage to PD 40 utilizing classification functionality 64, and class current source 120 is arranged to drive a predetermined current indicative of the power requirements of PD load circuitry 90 responsive to the presented classification voltage, thus indicating to PSE 60 the power requirements thereof. The amount of current is detected by classification functionality 64. Optionally, PSE 60 further provides PD 40 with information regarding the powering ability of PSE 60 by providing a plurality of classification events separated by mark events, with the information provided by the number of classification events. The mark events function to define the individual classification events. A class event counter, if supplied, is arranged to count the classification events and output information regarding the counted classification events to PD load circuitry 90, thus providing PD load circuitry 90 with information regarding the powering ability of the PSEs 60.
Each PSE 60 is further arranged, in the event that sufficient power is available to support the power requirements detected and output by classification functionality 64, to provide operating power for PD 40 over the respective associated set of twisted wire pairs 30 of structured cable 35 by raising the voltage above the classification voltage range responsive to powering functionality 66. First and second diode bridges 65 are each arranged to ensure that power received by PD interface 70 and PD load circuitry 90 is at a predetermined polarity irrespective of the connection polarity of PSE 60. UVLO circuit 100 is arranged to maintain isolation between PSE 60 and PD load circuitry 90 until a predetermined operating voltage has been achieved across PD interface 70, and upon sensing the predetermined operating voltage UVLO circuit 100 is further arranged to assert output PG thus closing electronically controlled switch 80 thereby providing power to PD load circuitry 90. Optionally, a timer (not shown) may be provided to ensure that the startup phase is complete prior to closing electronically controlled switch 80.
The current provided to PD 40 by each PSE 60 flows back through sense resistor RS on the return path. Powering functionality 66 is arranged to enable current flow through NMOSFET CL responsive to master control 63 and detect the magnitude of the current flowing through sense resistor RS. In the event that the detected current magnitude is greater than, or equal to, the predetermined current value, powering functionality 66 is arranged to reduce the gate voltage of NMOSFET CL, thereby preventing the magnitude of the current flowing therethrough from exceeding the predetermined current value. Thus, powering functionality 66 controls the power provided to PD 40 according to the detected class thereof. MPS detection functionality 68 is arranged to monitor the current flow through sense resistor RS and to instruct control circuitry 61 to open NMOSFET CL in the event that the current falls below a predetermined minimum over a predetermined time window, thus ending the powering cycle.
FIG. 1C illustrates a high level block diagram of a PoE powering arrangement 200, according to the prior art, which is in all respects identical PoE powering arrangement 10 with the exception that a first and a second PD interface 70 are provided, first PD interface 70 is connected so as to presented to first PSE 60 in accordance with ALT-A powering and second PD interface 70 is connected so as to presented to second PSE 60 in accordance with ALT-B powering. The outputs of first and second PD interface 70, after the respective electronically controlled switch 80 are shown as being connected together, however that is not meant to be limiting in any way, and PD load circuitry 90 may be arranged to accept connections from each of first and second PD interfaces 70 without exceeding the scope.
PoE powering arrangements 10 and 200 each provide power over four twisted wire pairs to a high power PD, however the prior art does not provide for a method for determining as to whether PoE powering arrangement 10, or PoE powering arrangement 200 is provided. For example, in the detection phase, if a valid signature resistor is detected by each of first and second PSE 60, it may be powering arrangement 10 wherein a single PD interface 70 is provided, or powering arrangement 200 wherein separated PD interfaces 70 are provided for each of ALT-A and ALT-B.